This invention relates in general to integrated circuit devices and more particularly, to integrated circuit devices having dummy features.
Polishing is used to planarize surfaces in forming integrated circuit devices. Traditionally, no tiling has been used in forming integrated circuit devices. When no tiling is used, polishing causes dishing or other problems related to non-uniform thickness across an integrated circuit device substrate. These problems include exceeding the depth of focus for lithography or etch related concerns.
Dummy features have been used in an attempt to solve the problems related to dishing and other accumulated thickness effects. Dummy features used to aid polishing are formed by xe2x80x9ctilingxe2x80x9d because, from a top view of the integrated circuit device, the pattern of dummy features looks like tiles. The process for tiling typically includes creating a circuit layout, defining a buffer zone (typically in a range of approximately 1-10 microns) around active features within the layout, and combining the circuit layout with the minimum zone to determine excluded areas. All other areas are available for tiling.
Regardless of circuit density, tiling is used if the distance between any of the active features is at or above a minimum width except for certain exclusion zones. Typically, the minimum width is no more than 10 microns, and can be approximately 10 microns. Tiles or at least partial tiles are placed in available areas at least 5 microns wide. The tiling pattern (i.e. size and density of tiles) is usually the same across the integrated circuit device. See FIG. 5 in each of U.S. patent application Ser. No. 5,278,105 and European published patent application number 0 712 156 (1996). Although portions of tiles are missing, the same feature density is used.